Memory cells (e.g., floating-gate transistors or PCRAM cells) are typically arranged in an array connected to a grid formed by a plurality of Word lines and Bit lines. The Word lines are generally parallel to one another and perpendicular to the Bit lines. Each of the memory cells forms a node of the array, and each node is connected to a particular pair of Word lines and Bit lines. In operation, each memory cell may be individually accessed by energizing a particular pair of Word lines and Bit lines while floating or oppositely biasing the rest of the Word lines and Bit lines.
The conventional arrangement of the memory array, however, cannot accommodate more than one memory cell per node. If the memory array includes two memory cells per node that are connected to a pair of Word lines and Bit lines, energizing the pair of Word lines and Bit lines would simultaneously energize the two parallel memory cells. Thus, the two memory cells may not be individually addressed or accessed. Accordingly, certain improvements to the memory arrays may be needed to accommodate more than one memory cell per node.